1. Field of the Invention
This present invention relates to a semiconductor device in which metal-insulator semiconductor (MIS) transistors are formed in a semiconductor layer provided on an insulating film. More particularly the invention relates to a semiconductor device that has a strained semiconductor layer and to a method of manufacturing this semiconductor device.
2. Description of the Related Art
Metal-oxide semiconductor (MOS) field-effect transistors (hereinafter referred to as MOSFETs) fabricated on a silicon-on-insulator (SOI) substrate have a low junction capacitance. Therefore, they are fit for use in high-speed LSIs and low-power-consumption LSIs. Any Si layer epitaxially grown on an SiGe layer has a crystal structure that is strained because of the difference between its lattice constant and that of the SiGe layer. MOSFETs fabricated on such a strained Si layer are suitable for use in high-speed LSIs since the mobility increases as the band structure modulates.
SOI-MOSFETs, each comprising such a SOI substrate and such a strained layer as described above, are elements more suitable for use in high-speed, low-power-consumption LSIs. (See Toshinori Numata, Toshifumi Irisawa, Tsutomu Tezuka, Junji Koga, Norio Hirashita, Koji Usuda, Eiji Toyoda, Yosiji Miaymura, Akihiko Tanabe, Naoharu Sugiyama, and Shinichi Takagi, “Performance enhancement of partially and fully-depleted strained-SOI MOSFETs and characterization of stained-Si device parameters” IEDM Tech. Dig., pp. 177-180, December 2004.)
The SOI-MOSFET is manufactured as follows. First, a lattice-relaxed SiGe layer is formed on a buried insulating film provided on an Si substrate. Then, a strained Si layer is formed on the SiGe layer. Subsequently, a gate electrode is formed on the strained Si layer, and a source and a drain are formed in the strained Si layer. Since the strained Si layer has been epitaxially grown on the SiGe layer, it has tensile stress acting along two axes that are parallel to the upper surface of the substrate.
Strained SOI-MOSFETs of this type are disadvantageous in the following respects. Unless the SiGe layer has high Ge composition, the strained Si layer cannot acquire sufficiently high hole mobility. If the Ge composition of the SiGe layer is too high, the SiGe layer and the strained Si layer can hardly maintain good crystallinity. The thinner the SOI film, the more prominently the short-channel effect can be controlled. If the SOI film is made thin, however, its parasitic resistance will increase. Moreover, since the SOI structure has a prominent self-heating effect, the thermal hysteresis of the LSI brings forth a great performance variation between the strained SOI-MOSFETs.
The SOI structure undergoes a specific phenomenon that some layers float from the substrate. Particularly, a phenomenon, such as kink phenomenon, hysteresis effect or pass-gate effect, makes it necessary to change the circuit design. In view of this, the conventional bulk-Si circuit should be changed in terms of design. Further, the SOI structure is disadvantageous in that the drain has but a low voltage endurance.
Thus, the conventional SOI-MOSFET is disadvantageous in some respects. First, the SiGe layer and the Si layer will be degraded in crystallinity if the SiGe layer has a high Ge composition to enhance the hole mobility in the strained Si layer. Second, if the SOI film is thin enough to control the short-channel effect, its parasitic resistance will increase. Third, its performance greatly varies because the SOI structure has a prominent self-heating effect.